The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to an EPROM data output interface that eliminates the need for back-end wait states and data hold logic when used with high speed microprocessors.
2. Discussion of the Prior Art
When EPROMs were originally developed, they were used in applications that were based either on single chip microcontrollers and microcomputers or on larger multi-chip computer systems. At that time, a standard output interface was adopted for transferring data from EPROM storage onto the system data bus. Although the standard interface still provides efficient interfacing with existing low-performance, single-chip microcontrollers, a significant mismatch has developed between the EPROM and high-speed, single-chip microprocessors, such as Motorola's MC68030/MC68040 and Intel's I386/I486 machines.
Existing EPROMs are parallel access memories with either 8-bit or 16-bit data word width and control signals comprising Chip Enable CE, Output Enable OE, and other signals that control programming, supply power and data direction. Since an EPROM is normally used only in the READ (data output) mode, only the signals associated with the READ mode will be defined for purposes of this discussion.
FIG. 1 shows a timing diagram of an existing EPROM in the read mode. In FIG. 1, hold time t.sub.DH is the time during which data is guaranteed valid after either the Chip Enable CE signal or the Output Enable OE signal returns to an inactive (high) state. For existing EPROMs, the industry standard guarantees a hold time t.sub.DH =0 nanoseconds. That is, according to the industry standard, as soon as either the Chip Enable or the Output Enable signal goes inactive, data at the outputs is assumed to be invalid.
Furthermore, after the Chip Enable signal or the Output Enable signal goes inactive, a float time t.sub.DF is required until the data lines are guaranteed to be in the High-Z (impedance) state, thus insuring that the data bus is available for use by the associated microprocessor. Existing EPROMs guarantee a float time of no less than 30 seconds. For high-speed microprocessors (faster than 20 MHz clock rate), this means that "wait states" are required at the end of an EPROM access to insure bus availability. This slows down system operation.
FIG. 2 shows conventional data output interface circuitry for controlling EPROM read operations. In the FIG. 2 circuitry, although the primary purpose of resistors R.sub.A and R.sub.B is to control the turn-on rate at the data outputs, these resistors also slow down the turn-off rate, thus increasing the float time t.sub.DF. As stated above, the FIG. 2 circuit makes no provision for a hold time t.sub.DH greater than zero.
An alternative prior art implementation places resistors R.sub.A and R.sub.B internal to the NAND and NOR gates such that only the turn-on rate is controlled and the turn-off rate is faster. The disadvantage of this approach is that turn-on control is not very exact.